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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4031B MSI 64-stage static shift register
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
64-stage static shift register
DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL load. Data from DA or DB, as determined by the state of A/B, is shifted into the first shift register position and all the data in
HEF4031B MSI
the register is shifted one position to the right on the LOW to HIGH transition of CP. DA is selected by a LOW, and DB by a HIGH on A/B. Registers can be cascaded either by connecting all CP inputs together or by driving CP of the most right-hand register with the system clock and connecting CO to CP of the preceding register. When the second technique is used in the recirculating mode, a flip-flop must be used to store O63 of the most right-hand register until the most left-hand register is clocked.
Fig.1 Functional diagram.
PINNING DA, DB A/B CP CO O63 O63 data inputs data select input clock input (LOW to HIGH edge-triggered) buffered clock output buffered output from the 64th stage complementary buffered output from the 64th stage
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
HEF4031BP(N): HEF4031BD(F): HEF4031BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
January 1995
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Philips Semiconductors
Product specification
64-stage static shift register
HEF4031B MSI
Fig.3 Logic diagram.
DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (c) VDD V Output (source) current HIGH; O63 HIGH; O63 Output (sink) current LOW; O63 5 10 15 5 4,75 10 15 VOH V 4, 6 9,5 13,5 2,5 0,4 0,5 IOL 1,5 -IOH -IOH VOL V SYMBOL -40 + 25 MAX. MIN. 0,65 2,0 6,5 2,0 1,8 6,3 16,0 + 85 MAX. mA mA mA mA mA mA mA
MIN. MAX. MIN. 1,0 3,0 10,0 3,0 2,7 9,5 24,0 0,85 2,5 8,5 2,5 2,3 8,0 20,0
January 1995
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Philips Semiconductors
Product specification
64-stage static shift register
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP O63 HIGH to LOW 5 10 15 5 LOW to HIGH CP O63 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CP CO HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times; O63 HIGH to LOW LOW to HIGH Output transition times; O63, CO HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL 180 65 45 170 65 45 190 75 50 190 75 50 70 35 25 55 30 25 25 12 8 40 20 13 60 30 20 60 30 20 360 ns 130 ns 90 ns 340 ns 130 ns 90 ns 380 ns 150 ns 100 ns 380 ns 150 ns 100 ns 140 ns 70 ns 50 ns 110 ns 60 ns 50 ns 50 ns 24 ns 16 ns 80 ns 40 ns 26 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns SYMBOL MIN. TYP. MAX.
HEF4031B MSI
TYPICAL EXTRAPOLATION FORMULA 167 ns + (0,26 ns/pF) CL 57 ns + (0,16 ns/pF) CL 40 ns + (0,11 ns/pF) CL 148 ns + (0,45 ns/pF) CL 56 ns + (0,19 ns/pF) CL 39 ns + (0,13 ns/pF) CL 163 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 163 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 43 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 28 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 5 ns + (0,40 ns/pF) CL 3 ns + (0,18 ns/pF) CL 2 ns + (0,13 ns/pF) CL 8 ns + (0,65 ns/pF) CL 5 ns + (0,30 ns/pF) CL 3 ns + (0,20 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
January 1995
4
Philips Semiconductors
Product specification
64-stage static shift register
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Set-up times DA , DB CP 5 10 15 5 A/B CP Hold times DA, DB CP 10 15 5 10 15 5 A/B CP Minimum clock pulse width; LOW Maximum clock pulse frequency 5 10 15 5 10 15 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 4000 fi + (foCL) x VDD 2 19 000 fi + (foCL) x VDD 54 000 fi + (foCL) x VDD
2 2
HEF4031B MSI
SYMBOL
MIN. TYP. MAX. 25 0 -5 -10 10 0 -5 10 10 10 10 10 10 90 35 25 5 14 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
TYPICAL EXTRAPOLATION FORMULA
tsu
25 10 30
tsu
15 10 40
thold
40 40 40
see also waveforms Fig.4
10 15
thold
40 40 180
tWCPL
70 50 2,5
fmax
7 10
where fi = input freq. (MHz) fo = output freq. (MHz) CL =load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
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Philips Semiconductors
Product specification
64-stage static shift register
HEF4031B MSI
Fig.4
Waveforms showing minimum clock pulse width, set-up and hold times for DA, DB to CP and A/B to CP. Set-up and hold times are shown as positive values but may be specified as negative values.
APPLICATION INFORMATION An example of an application for the HEF4031B is: * Serial shift register.
January 1995
6
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(1) Recirculating input. (2) Mode control: VDD = recirculation; ground (VSS) = new data.
APPLICATION INFORMATION
Philips Semiconductors
64-stage static shift register
Fig.5 Cascading using direct clocking for high speed operation (see clock rise and fall time requirements).
7 Product specification
(1) Recirculating input. (2) Mode control: VDD = recirculation; ground (VSS) = new data. (3) For recirculation mode only, FF to delay data until first register delayed clocking has occurred. (4) Delayed clock-to-clock; new data into first register.
HEF4031B MSI
Fig.6 Cascading using delayed clocking for reduced clock drive requirements.

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